Anand S Moghe (He has trained several engineers in VLSI under the DDUGKY scheme of Govt of India).
Online Course 1 : Digital Design & Verilog HDL
"SemiconLabs' New Online Course"
1. Combinational Logic.
2. Sequential Logic: Types of flip-flops, conversion between different types of FFs, counters & freq dividers, FSMs, timing analysis.
3. Verilog HDL: RTL coding and verification
Course Fee : Contact Us For Details.
Regular Course 1 : ASIC Physical Design
VLSI Back-End course covers the following broad areas: (Cadence /Synopsys Tools will be used)
1. Digital Design: Combinational Logic and Sequential Logic
3. Macro / SC Based layout Techniques
4. DRC / ERC
5. Parasitic Extraction & Routing delays
6. TCL scripting
Course Fee : Rs 1,00,000/- (One Lakh Rupees )
Regular Course 2 : ASIC Verification
VLSI Front-End course covers the following broad areas: (Cadence / Mentor Graphics tools will be used)
1. Basic Engineering Circuit Analysis
2. Digital Design: Combinational Logic and Sequential Logic with Timing analysis
3. Verilog HDL
4. System Verilog & DFT basics
5. PERL scripting / C-shell scripting
Course Fee : Rs 1,00,000/- (One Lakh Rupees)